1. Technical Field
This disclosure relates to electronic design automation (EDA). More specifically, this disclosure relates to methods and apparatuses for global timing modeling within a local context.
2. Related Art
Conventional circuit optimization techniques update timing of the entire design (e.g., from timing start-points to timing end-points) whenever a logic gate is changed. Updating arrival and required times for the entire design is computationally expensive. As a result, the timing update operation often becomes a runtime bottleneck in conventional synthesis optimization systems (e.g., logic synthesis and physical synthesis).
To combat the runtime bottleneck problem, conventional techniques typically impose a time limit on the optimization process. Although this approach ensures that the optimization process is guaranteed to terminate within the predetermined amount of time, it results in poor Quality-of-Results (QoR). Hence, what is needed are efficient circuit optimization techniques which produce good QoR, without incurring a lot of computational runtime.